1. Field of the Invention
The present invention relates generally to semiconductor integrated circuit apparatus and, more particularly, to a semiconductor integrated circuit apparatus including a supply voltage conversion circuit.
2. Description of the Background Art
In recent years, semiconductor elements in semiconductor integrated circuit apparatus have been reduced in scale in order to increase the operation speed and the integration of the semiconductor integrated circuit apparatus.
With reduction in the scale of MOS transistors, for example, the gate length of the MOS transistors has been decreased. However, if the gate length of the MOS transistors is shorter, hot electrons are liable to be captured into a gate oxide film of the MOS transistors in use. The capture of the hot electrons into the gate oxide film causes a degradation in the reliability of the MOS transistors.
As a higher voltage is applied to the MOS transistors, the hot electrons are more liable to be captured into the gate oxide film. Normally, a supply voltage of 5 V is applied to semiconductor integrated circuit apparatus at present. If the 5 V supply voltage is applied to the smaller-scale MOS transistors, however, the phenomenon that the hot electrons are captured into the gate oxide film becomes prominent.
Thus, such an approach has been made that a voltage lower than a normal supply voltage is applied to the smaller-scale MOS transistors. This approach is realized by provision of a supply voltage conversion circuit for lowering an external supply voltage (5 V) within semiconductor integrated circuit apparatus.
More specifically, the voltage lowered by the supply voltage conversion circuit is applied as a driving voltage to a circuit including the smaller-scale MOS transistors in the semiconductor integrated circuit apparatus.
FIG. 11 shows a simplification of the structure of a DRAM (Dynamic Random Access Memory) described in IEEE Journal of Solid-State Circuits, vol. 24, No. 5 (October 1989), pp. 1170-1175 as one example of semiconductor integrated circuit apparatus including a supply voltage conversion circuit.
Description will now be made on the structure of a conventional semiconductor integrated circuit apparatus including a supply voltage conversion circuit with reference to FIG. 11.
A DRAM chip 1 includes a supply voltage conversion circuit VDC, an internal circuit ICKT driven by an output of supply voltage conversion circuit VDC, and an output driver OD directly driven by a supply voltage Vext externally applied to DPAM chip 1.
Supply voltage conversion circuit VDC lowers external supply voltage Vext to a constant voltage. This constant voltage is called an internal supply voltage Vint as compared with external supply voltage Vext. Internal supply voltage Vint is applied to internal circuit ICKT.
DRAM chip 1 externally receives supply voltage Vext and a ground potential Vss (=0 V) at a power supply terminal Tcc and a ground terminal Tss, respectively.
FIG. 12 is a circuit diagram showing one example of supply voltage conversion circuit VDC.
Referring to FIG. 12, this supply voltage conversion circuit includes a generator 300, a regulator 400, and an N channel MOS transistor Qc having its gate receiving an output of regulator 400. An external supply voltage Vext is applied to a source of transistor Qc, and a drain output of transistor QC is employed as an internal supply voltage Vint.
This supply voltage conversion circuit is described in IEEE J. Solid-State Circuits, vol. SC-18, pp. 463-470 (October 1983).
Generator 300 includes two diode-connected N channel MOS transistors Qa and Qb, a capacitor Ca, and a ring oscillator 310 driven by external supply voltage Vext for generating a pulse signal with a constant period.
Regulator 400 includes four N channel MOS transistors Qd, Qe, Qf and Qg and a resistance element Rb which are connected in series with each other between the gate of transistor Qc and a ground terminal Tss, a capacitor Cb connected to the gate of transistor Qc, an N channel MOS transistor Qh connected between the gate of transistor Qc and ground terminal Tss, and a resistance element Ra. Each of those four transistors Qd, Qe, Qf and Qg is diode-connected.
Transistors Qa and Qb and resistance element Ra are connected in series with each other between a supply terminal Tcc and the gate of transistor Qc. Capacitor Ca is provided between an output terminal of ring oscillator 310 and a connecting point between transistors Qa and Qb. Transistor Qh has its gate connected to a connecting point between transistor Qg and resistance element Rb.
With a power supply turned on, external supply voltage Vext becomes higher than a potential corresponding to a sum of a threshold voltage of transistor Qa and that of transistor Qb. Accordingly, transistors Qa and Qb are turned on, so that capacitor Cb is charged by a current supplied via transistors Qa and Qb and resistance element Ra from supply terminal Tcc. This raises a potential on the gate (a node Nb) of transistor Qc.
If external supply voltage vext is of an inherent magnitude (normally 5 V), the potential on node Nb reaches a potential corresponding to a sum of respective threshold voltages of the four N channel MOS transistors, so that all transistors Qd, Qe, Qf and Qg are turned on.
If the potential on node Nb is approximately the same as the potential corresponding to the sum of the respective threshold voltages of four transistors Qd, Qe, Qf and Qg, little current flows through resistance element Rb, resulting in a small voltage drop on resistance element Rb. Thus, the potential of the gate (a node Nc) of transistor Qh does not exceed the threshold voltage of transistor Qh, and hence transistor Qh is in an OFF state.
However, if the increase in external supply voltage Vext causes the potential on node Nb to rise to the potential corresponding to the sum of the respective threshold voltages of five transistors Qd, Qe, Qf, Qg and Qh, then the current flowing through resistance element Rb increases, so that the potential on node Nc attains the threshold voltage of transistor Qh. Accordingly, transistor Qh is turned on, so as to decrease the potential on node Nb. If the potential decrease causes the potential on node Nb to be lowered again to around the potential corresponding to the sum of the threshold voltages of four transistors Qd, Qe, Qf and Qg, then transistor Qh is again turned off. Thus, the potential on node Nb is maintained at around the potential corresponding to the sum of the respective threshold voltages of four transistors Qd, Qe, Qf and Qg.
Conversely, if external supply voltage vext decreases for some causes and then the potential on node Nb becomes lower than the potential corresponding to the sum of the respective threshold voltages of four transistors Qd, Qe, Qf and Qg, since at least any one of these four transistors is in the OFF state, the potential on node Nb is no longer maintained by five transistors Qd-Qh. In this case, however, the potential on node Nb is compensated by generator 300.
During the period for which an output potential of ring oscillator 310 is at a high level (corresponding to external supply voltage Vext), since coupling of capacitor Ca increases a potential on a node Na, transistor Qa is turned off and transistor Qb is turned on, so as to supply charges from node Na to capacitor Cb. During the period for which the output potential of ring oscillator 310 is at a low level (corresponding to a ground potential Vss), since transistor Qa is turned on by discharging of capacitor Ca, to increase the potential on node Na. Thus, transistor Qb is also turned on, so that charges are supplied via transistors Qa and Qb to capacitor Cb. In such a circuit operation (hereinafter referred to as a charge pumping operation), the potential on node Nb becomes a slightly higher potential than external supply voltage Vext, and consequently a drain potential Vint of transistor Qc becomes approximately the same potential as external supply voltage Vext.
If the potential on node Nb becomes equal to or higher than the potential corresponding to the sum of the respective threshold voltages of four transistors Qd, Qe, Qf and Qg by such an operation of generator 300, then as described above, the potential on node Nb is maintained at around the potential corresponding to the sum of the threshold voltages of these four transistors by five transistors Qd-Qh.
In this manner, since the gate potential of transistor Qc is almost kept at a constant potential higher than the threshold voltage of transistor Qc under no influence caused by the change of external supply voltage Vext, the drain potential of transistor Qc, i.e., internal supply voltage vint is kept almost constant despite the change of external supply voltage Vext.
Internal circuit ICKT includes a memory cell array MCA, a control signal generating circuit CG, and a power-on reset signal generating circuit PORG.
Control signal generating circuit CG is driven by internal supply voltage Vint to generate an internal control signal for controlling predetermined circuits such as memory cell array MCA and output driver OD in response to externally applied control signals RAS, CAS and WE.
Memory cell array MCA includes a plurality of memory cells (not shown) arranged in matrix of rows and columns, and a data writing/reading circuit (not shown) for writing data into these memory cells and reading data from the memory cells. The data writing/reading circuit is controlled by a control signal from control signal generating circuit CG to write externally applied data Din into a memory cell designated by an external address signal Add and read the data from the memory cell designated by external address signal Add.
Output driver OD is controlled by a control signal from control signal generating circuit CG to convert a voltage signal of the data read from the memory cell into a signal of a predetermined voltage level. This converted signal is final output data Dout.
In general, the basis of a determination of the logic level of an output data signal Dout is normalized, wherein a voltage not lower than 2.4 V is regarded as of a high level (corresponding to a logic value "1"), and a voltage not higher than 0.4 V is regarded as of a low level (corresponding to a logic value "0"). Thus, output driver OD amplifies a voltage applied as read data from memory cell array MCA so as to conform with this normalization.
Immediately after external supply voltage Vext is applied to DRAM chip 1, power-on reset pulse generating circuit PORG generates a one-shot pulse of a high level (or a low level) to initialize control signal generating circuit CG.
Power-on reset signal generating circuit PORG is provided to force a potential on a predetermined node to a potential which should be applied upon the initiation of the operation of DRAM chip 1 (hereinafter referred to as the initial potential) when external supply voltage Vext is applied to DRAM chip 1, i.e., DRAM chip 1 starts operating.
In order that such circuits as memory cell array MCA and output driver OD controlled by control signal generating circuit CG operate normally after the application of the external supply voltage to power supply terminal Tcc, an output potential of control signal generating circuit CG must be a predetermined potential at the time point when external supply voltage Vext is applied to supply terminal Tcc. Accordingly, a node (not shown) within control signal generating circuit CG, which determines the output potential of control signal generating circuit CG, must inevitably be at a potential which enables the output potential of control signal generating circuit CG to be the above-described predetermined potential, i.e., the initial potential immediately before the application of external supply voltage Vext to power supply terminal Tcc.
However, the node determining the output potential of control signal generating circuit CG includes a node (hereinafter referred to as the potential indefinite node), the potential of which is liable to be a potential different from the initial potential when no external supply voltage Vext is being applied to power supply terminal Tcc. Thus, power-on reset signal generating circuit PORG is provided in order to force the potential on the potential indefinite node to the initial potential immediately after the application of the external supply voltage to power supply terminal Tcc.
More specifically, control signal generating circuit CG is configured such that the initial potential is supplied to the potential indefinite node only during the period for which a one-shot pulse is being output from power-on reset signal generating circuit PORG. Accordingly, since the predetermined potential is absolutely output from control signal generating circuit CG immediately after the application of external power supply voltage Vext to power supply terminal Tcc, such various circuits as memory cell array MCA and output driver OD, controlled by control signal generating circuit CG, subsequently perform normal operations.
Description will now be made on the structure and operation of a conventional power-on reset signal generating circuit by reference to FIGS. 13A and 14. It is assumed in the following description that all nodes in the power-on reset signal generating circuit are at 0 V when a power supply is turned on. FIG. 13A shows the configuration of a power-on reset signal generating circuit disclosed in U.S. Pat. No. 4,818,904 as one example of the power-on reset signal generating circuit PORG of FIG. 11. FIG. 14 is a waveform diagram showing the operation of the power-on reset signal generating circuit of FIG. 13A.
Referring to FIG. 13A, this power-on reset signal generating circuit includes a capacitor 10 connected to a terminal Tint receiving a supply voltage Vcc, an N channel MOS transistor 8 connected in series to capacitor 10, a latch circuit LAT connected to a node N1 between capacitor 10 and transistor 8, inverters 4 and 5 and a diode array DA connected between node N1 and a gate of transistor 8.
A potential on a node N3 between inverter 5 and diode array DA serves as an output POR of this power-on reset signal generating circuit.
An N channel MOS transistor 9 having its gate receiving a potential on a node N2 between transistors 4 and 5 is connected to the gate of transistor 8.
Latch circuit LAT includes an inverter 2 for inverting a potential on node N1, and an inverter 3 for inverting a potential of inverter 2 to apply the inverted potential to node N1.
Diode array DA includes diode-connected N channel MOS transistors 6 and 7.
An output terminal of inverter 2 and the gate of transistor 8 are grounded via capacitors 11 and 12, respectively.
When supply voltage Vcc is applied to the power-on reset signal generating circuit at a time t1 of FIG. 14, the potential on node N1 (FIG. 14(b)) rises to a high level due to coupling of capacitor 10, following a rise of supply voltage Vcc (FIG. 14(a)) to a high level.
Inverter 4 inverts the high level potential on node N1 to supply a low level potential to node N2. Inverter 5 further inverts the low level potential on node N2 to supply the inverted potential to node N3. Thus, the potential on node N3 (FIG. 14(d)) rises to a high level in response to the supply of power.
During the period for which the potential on node N2 is being at a low level, since transistor 9 is in an OFF state, a potential of the gate of transistor 8 (a node N4) is determined on the basis of the potential on node N3. More specifically, if the potential on node N3 is lower than a potential corresponding to a sum of respective threshold voltages of transistors 6 and 7, at least one of transistors 6 and 7 is in the OFF state, and hence capacitor 12 is not charged, so that the potential on node N4 is kept at 0 V. If the potential on node N3 attains the potential corresponding to the sum of the respective threshold voltages of transistors 6 and 7, however, both transistors 6 and 7 are turned on. Accordingly, a potential which is lower than the potential on node N3 by the sum of the respective threshold voltages of transistors 6 and 7 is supplied to node N4 while capacitor 12 is being charged by charges supplied from node N3. Thus, the potential on node N4 starts slowly rising slightly later than the rise of the potential on node N3, as shown in FIG. 14(e).
If the potential on node N4 is lower than the threshold voltage of transistor 8, the potential on node N1 is kept at a high level since transistor 8 is in the OFF state.
When the potential on node N4 reaches the threshold voltage of transistor 8, the potential on node N1 is lowered to a ground potential, i.e., a low level potential since transistor 8 is turned on. Accordingly, the potential on node N1 changes from a high level to a low level as shown in FIG. 14(b) at the time point when the potential on node N4 exceeds the threshold voltage of transistor 8 after the potential on node N3 rises to a high level.
If the potential on node N1 changes to a low level, the potential on node N2 changes from a low level to a high level as shown in FIG. 14(c) by the inversion operation of inverter 4. Also the potential on node N3 subsequently changes by the inversion operation of inverter 5.
Accordingly, the potential on node N3 is, as shown in FIG. 14(d), once attains a high level in response to the supply of power at time t1, and then again falls to a low level at a time t2 when the potential on node N4 reaches the threshold voltage of transistor 8.
If the potential on node N2 attains a high level, the potential on node N4 returns again to 0 V by discharging of capacitor 12 since transistor 9 is turned on. (See FIG. 14(e))
Accordingly, since the potential on node N4 again becomes lower than the threshold voltage of transistor 8 at and after time t2, node N1 is no longer supplied with a ground potential via transistor 8.
However, when transistor 8 is rendered conductive, if the potential on node N1 attains 0 V, an output potential of inverter 2 attains a high level, and hence capacitor 11 is charged. Accordingly, a potential on the output terminal of inverter 2 is kept at a high level. Inverter 3 inverts the output potential of inverter 2 to supply the inverted potential to node N1. Consequently, the potential on node N1 is kept at 0 V also after transistor 8 returns to the OFF state.
As described above, since the potential on node N1 is kept at a low level potential after it once falls to that potential, the potential on node N3 is also fixed at a low level after it falls that low level at time t2. That is, a one-shot pulse of a high level is generated from this power-on reset signal generating circuit only once in response to the supply of power.
When the power-on reset signal generating circuit of FIG. 13A is employed as power-on reset signal generating circuit PORG of FIG. 11, internal supply voltage Vint is used as supply voltage Vcc, and capacitors 11 and 12 and transistors 8 and 9 are connected to ground terminal Tss to receive ground potential Vss. Then, a potential on the potential indefinite node within control signal generating circuit CG is forced to the initial potential in response to the one-shot pulse shown in FIG. 14(d).
FIG. 15 is a diagram showing one example of a circuit to be initialized by the power-on reset signal generating circuit. FIG. 15 illustrates a circuit configuration in the case where an output of the power-on reset signal generating circuit is such a high level one-shot pulse as shown in FIG. 14(d).
Referring to FIG. 15, it is assumed that when power is supplied, respective potentials on respective output terminals N10 and N11 of two NAND gates 100 and 101 constituting a flipflop FL must be at a high level and a low level, respectively.
When NAND gate 100 does not receive an output of an inverter 102, NAND gate 100 is a 2-input NAND gate which receives as an input only a predetermined control signal .phi.1 and an output signal of NAND gate 101. On the other hand, NAND gate 101 is a 2-input NAND gate which receives as an input a predetermined control signal .phi.2 different from control signal .phi.1 and an output signal of NAND gate 100. Control signal .phi.1 is a set signal for setting this flipflop, while control signal .phi.2 is a reset signal for resetting the flipflop.
When a potential of control signal .phi.1 and that of control signal .phi.2 are at a high level and a low level, respectively, an output potential of NAND gate 101 attains a high level independently of an output potential of NAND gate 100. Thus, both input potentials to NAND gate 100 attain a high level. Consequently, an output signal of NAND gate 100, which is an output signal of this flipflop FL, attains a low level. In other words, a logic value "1" is set in a node N11 in flipflop FL.
Conversely, when the respective potentials of control signals .phi.1 and .phi.2 are at a low level and a high level, the output potential of NAND gate 100 attains a high level independently of the output potential of NAND gate 101. Thus, both input potentials to NAND gate 101 attain a high level, and hence the output potential of NAND gate 101 attains a low level. That is, in this case, a node N11 in flipflop FL is reset in a logic value "0".
When both the potentials of control signals .phi.1 and .phi.2 are at a high level, the output potential of NAND gate 100 is determined on the basis of the output potential of NAND gate 101. Similarly, the output potential of NAND gate 101 is determined on the basis of the output potential of NAND gate 100. Thus, in this case, the respective output potentials of NAND gates 100 and 101 are kept at the same logic level as so far. For example, if both of the potentials of control signals .phi.1 and .phi.2 attain a high level after a potential on a node N10 is made definite by attainment of only one of control signals .phi.1 and .phi.2 to a high level, then the potential on node N10 is kept at that definite potential.
However, respective potentials on nodes N10 and N11 are not made definite at any logic level during the period for which no power is being supplied. Thus, if both the potentials of control signals .phi.1 and .phi.2 attain a high level immediately after the supply of power, the potentials on nodes N10 and N11 become indefinite.
However, if a 3-input NAND gate is used as NAND gate 100, and an output signal POR of the power-on reset signal generating circuit as well as the output potential of NAND gate 101 and control signal .phi.1 is input via inverter 102 to this 3-input NAND gate, then the respective potentials on nodes N10 and N11 upon the supply of power are made definite at the initial potential.
Soon after the power supply is turned on, output signal POR of the power-on reset signal generating circuit is at a high level for a definite period, and hence inverter 102 supplies a potential which is at a low level for a definite period to NAND gate 100. Thus, the output potential of NAND gate 100 attains a high level independently of the output potential of NAND gate 101 and that of control signal .phi.1. Accordingly, since both input potentials to NAND gate 101 attain a high level, the output potential of NAND gate 101 attains a low level.
Therefore, if the length of the period for which output signal POR of the power-on reset signal generating circuit is being at a high level is not shorter than the time period required until the potential on node N10 is completely made definite at a high level by the output signal of NAND gate 100, then the respective potentials on nodes N10 and N11 serving as potential indefinite nodes are set to the initial potential immediately after the power supply is turned on.
In this manner, the use of the output of the power-on reset signal generating circuit enables the potential on the potential indefinite node to be forced to the initial potential soon after the power supply is turned on.
Such a power-on reset signal generating circuit is widely used in a semiconductor memory device.
While the output of power-on reset signal generating circuit PORG is supplied only to control signal generating circuit CG in FIG. 11, this output is in fact supplied also to potential indefinite nodes of other circuits not shown.
In accordance with the conventional semiconductor integrated circuit apparatus including the power-on reset signal generating circuit, however, there is a case where the power-on reset signal generating circuit outputs no one-shot pulse having a sufficient pulse width and a level for ensuring that a predetermined potential indefinite node is forced to be set in an initial potential.
FIG. 16 is a waveform diagram showing one example of variations of external supply voltage Vext and an output signal of the power-on reset signal generating circuit in the conventional semiconductor integrated circuit apparatus. In FIG. 16(b), a potential waveform which should inherently be output from the power-on reset signal generating circuit is denoted by dotted lines.
Referring to FIG. 16, when external power is supplied to the semiconductor integrated circuit apparatus at a time t3, external supply voltage Vext (FIG. 16(a)) rapidly rises to 5 V, whereas an output (FIG. 16(b)) of the power-on reset signal generating circuit starts slowly rising slightly later than time t3 when the power supply is turned on, but returns to 0 V before it rises to a constant voltage (normally 3-4 V) obtained when supply voltage conversion circuit VDC lowers external supply voltage Vext.
Although it has been unclear why such a phenomenon occurs, the conventional semiconductor integrated circuit apparatus provides the following disadvantages due to the fact that no normal one-shot pulse is obtained from the power-on reset signal generating circuit.
Unless any normal one-shot pulse is obtained from the power-on reset signal generating circuit immediately after the power supply is turned on, a potential indefinite node is not set in an initial potential upon starting of the operation of the semiconductor integrated circuit apparatus.
Referring to FIG. 15, for example, if the potential of output POR of the power-on reset signal generating circuit is at a low level immediately after the supply of power, the output potential of inverter 102 is still at a high level even soon after the supply of power. Thus, even after the power supply is turned on, the output potential of NAND gate 100 remains indefinite, and consequently the output potential of NAND gate 101 also remains indefinite.
Further, if the period for which output signal POR of the power-on reset signal generating circuit is being at a high level is extremely short, then the output potential of inverter 102 attains a high level before the potential on node N10 completely attains a high level in response to the output potential of NAND gate 100. Thus, both the output potentials of NAND gates 100 and 101 become indefinite, and consequently neither of the potentials on nodes N10 and N11 are set to the initial potential.
Unless any potential indefinite node is set in the initial potential soon after the supply of power, a circuit which responds to the potential on this potential indefinite node does not subsequently perform a normal operation, resulting in malfunctions of the entire semiconductor integrated circuit apparatus.
With reference to FIG. 11, for example, unless any normal one-shot pulse is obtained from power-on reset signal generating circuit PORG, the potential indefinite node within control signal generating circuit CG is not set to the initial potential even if external supply voltage Vext is applied to power supply terminal Tcc. Thus, no signal having an expected potential is obtained from control signal generating circuit CG. Consequently, since the data writing/reading circuit does not subsequently perform normal data writing/reading operations in memory cell array MCA controlled by control signal generating circuit CG, a basic operation of DRAM chip 1 is not accomplished.